Low-power electronic devices typically include exceedingly complex clock circuits that are designed to reduce power dissipation while providing critical timing information to the various subsystems. To help reduce power dissipation, such systems typically implement clock gating. Clock gating, however, presents layout problems during scan insertion and clock tree balancing. For example, typical electronic design automation (EDA) and synthesis software tools allow the designer to balance the clock trees in only a single mode, requiring multi-pass clock tree generation. If a designer balances the clock tree in normal operation mode, and then in scan mode, in most cases the normal mode will no longer function properly. Similarly, if the scan mode is balanced first, and then normal mode is balanced, the scan mode will no longer operate (e.g., the clock skew may be prohibitively high).
Currently known methods of addressing this problem involve manually balancing clock trees to meet the design requirements. This means that, even after a minor change to the design, where a different place-and-route is required, the manual process has to be repeated, and there is still uncertainty as to whether the design requirements can be met. The result is an iterative, manual process, which is particularly undesirable from a time-to-market perspective.
This manual process also gives rise to convergence problems, which also delay the design process. Furthermore, currently known solutions are designed for a single product, and therefore cannot be transferred to other products.
Methods are therefore needed to solve these and other deficiencies of the prior art. More particularly, there is a need for a scan insertion methodology that can run substantially automatically, is portable to future devices, and is convergent.